Exemplary embodiments relate to a pipelined analog-to-digital converter.
An image system such as HDTV may necessitate an high-performance analog-to-digital converter (hereinafter, referred to as ADC) which provides a high resolution of 10 bits to 12 bits and a high sampling speed of some hundreds MHz. Among various ADC structures, a pipeline structure may have been used to satisfy high-speed signal processing and high-resolution conditions.
In case of a typical pipelined ADC, conversion stage offset and gain error of a conversion stage may be caused due to a conversion stage having capacitor mismatch and an insufficient DC voltage gain characteristic of an operational amplifier. To solve such problems, the typical pipelined ADC may cause power consumption of an operational amplifier, an increase in a realization area, and an increase in an area of a capacitor.